Validation of Fault Tolerance by Fault Injection in Vhdl Simulation Models*

This paper addresses the problem of the validation of fault-tolerant systems. It presents the preliminary results of a collaborative research aimed at providing an integrated environment for applying fault injection into simulation models encompassing various levels of abstraction. The expected benefits of the approach are clearly identified in relation to other fault injection methods available and the use of VHDL as the simulation language is motivated. Four techniques for injecting faults into VHDL models are described: two techniques require the modification of the VHDL model, while the other two rely on the commands available in the simulator to inject faults during the execution of the simulation; their respective merits are analyzed and compared. Finally, the main features of a tool for implementing all the considered techniques are outlined and the associated steps in the model generation and model execution phases are briefly described. * This work is performed within the framework of PDCS2, ESPRIT Basic Research Action n°6362, "Predictably Dependable Computing Systems".